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staff biographies
VR – SENIOR
TECHNICAL STAFF
MAJOR INTERESTS AND SKILLS
Equipment engineering and process
start-up. Process engineering, process integration development and
characterization. Yield enhancement, statistical analysis, SPC, DOE, device engineering, quality assurance.
EXPERIENCE
Over twenty years of
engineering experience as a semiconductor process engineer and consultant with
both US and Japanese companies encompassing AMLCD, DRAM,
SRAM, Gate Array and ASIC
technologies.
Recent experience
includes three years as Director of Technology, Manufacturing Engineering
Manager at Integrated Circuit Systems (Formally Micro Networks
Corporation). While at Integrated
Circuit Systems projects included:
Managing two manufacturing fabs: Auburn, NY
and Worcester, MA.
Implementing lean manufacturing, simplified operations. Introduced
6Sigma, Kaizen/events and Continuous Improvement methodologies. Supported
in-house courses (WPI) with QC/QA
department for all employees — speeding profitability.
Expertise in
Diffusion, CVD, Ion implant,
Photolithography, SOG, Wet and Dry Etch Techniques, metalization
and Silicon Epitaxy. Specialist in equipment – process
optimization for PECVD, RIE, ICP and plasma chemistry/physics. Experience in both mature Fabs and in start-up of wafer fabs,
R & D, and FPD operations.
Responsibilities included: Fab design; equipment selection, installation
and qualification; equipment engineering; process evaluation and qualification;
and materials and process specification writing. Authored several technical
books and training manuals on Plasma Etching Procedures, Statistical Process
Control and Design of Experiments; and has presented technical papers at IEEE
meetings. Holds two patents.
While at SONY, as
section head, was instrumental in setting up a state-of-the-art sub micron
wafer fab facility. Key Project Leader in OIS
AMLCD flat panel display manufacturing facility start-up, with responsibility
for process piping specification development and supervision of process piping
and fit-up. While at Intel, worked as a senior process engineer in plasma etch
and metallization, specializing in technology development in Fab 7. At VLSI
Technology, as section head, developed multilevel interconnection processes
including sloped contact RIE of doped LTO to thin doped poly gates and Si contacts
in their advanced, sub-micron feature fab. Was also responsible for device
engineering and testing. Instrumental in integrating the equipment maintenance
and process engineering groups into a coordinated work force oriented toward
yield enhancement and productivity. Earlier positions as section head at GTE
involved start-up of a 1.2 micron CMOS
line: and as process engineer at Motorola R&D Labs, was mainly responsible
for the Si Epitaxy area. Co-authored several of the
technical manuals required in establishing the Motorola training school for
engineers and technicians.
EDUCATION
BS Degree in Chemistry and Chemical
Engineering, Universidad Catholica de Chile
PhD in Physical Chemistry, Catholic University of America, Washington, DC
Post Doctoral Fellowships at Boston College
and Massachusetts Institute of Technology (MIT)
AGI Abbie Gregg,
Inc. | Engineering |
Consulting | Helping the world turn technology into
products.
1130 E. University Drive Suite 105 | Tempe, AZ 85281 USA | Phone: 480-446-8000 |
Fax: 480-446-8001 | www.abbiegregg.com