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staff biographies

RV - Senior Technical Staff, Process Integration /Electrical Engineering

MAJOR INTEREST AND SKILLS
Wafer fab start-up, process engineering, semiconductor product R&D, circuit design compatibility, process integration, device and yield enhancement engineering in wafer fabs, statistical process control implementation, parametric test optimization, reliability and quality engineering for both IC’s and packages, wafer fab design, wafer fab tool install, selecting and managing semiconductor foundry capacity. Intimately familiar with foundry situations in Asia

EXPERIENCE
3 years as a consultant supporting solid state product design, prototyping, front end fabrication and assembly. Expert in sensor driver chips and gate drivers. Additional consulting experience designing electrical systems for Unversity cleanrooms and laboratories including emergency power, grounding, and panel boards for US and European clients.

Extensive experience in both engineering management and program management. Proven track record in completing projects on time and on budget while working closely with all parties involved. Good motivator; positive, energetic and data driven work style. Fluent in Spanish.

As Manager of Fab Operations at Nitronex for 3 years, was responsible for process development of GaN film process on Si wafers. Key responsibilities included the deposition of GaN Films on 4 inch Si wafers and the eventual processing into High Frequency transistors for the cell phone base station market. Process and yield investigations completed included: determining if vertical or horizontal film deposition gave higher quality films of GaN, looking at whether TEG gave better films than TMG, looking into 6 inch wafers vs. 4 inch wafers and their deposition issues, investigating doping methods and sources for GaN, chemistries for etching GaN films and their effect on the electrical performance, processes for making contacts to the device, methods to electrically isolate the GaN transistor so edge effects were minimized, unique method of depositing gold for interconnects, gate optimization, and processing effects on the RF performance of the GaN device. Also evaluated methods of doing the electrical interconnects on GaN devices to determine which gave the best RF performance. Improved the purity of vendor supplied hydrogen, and gold plating solutions to ensure a good yield.

Also, as Manager of Fab Operations was responsible for testing devices to RF performance specs. Designed and built an RF test station to extract all the relevant design parameters and also perform reliability testing on a large group of devices to establish reliability history. This test structure allowed design of a matching network inside the transistor package to optimize the transistor’s RF performance.

Responsible for building a new compound semiconductor fab in North Carolina. Designed the fab, the tool placement and installation with an optimized product flow. Evaluated new tools needed and what tools from the development fab could be retained. The new fab was designed to be very flexible and could handle other compound semiconductor materials and processes.

Diversified background including 14 years with Motorola Inc. in various positions from individual contributor to Yield Engineering Manager. 7 years with Intel in engineering management roles responsible for device integration, quality and reliability.

As Sr. Manager Engineering, Operations for Silterra PCL Kulim Malaysia , helped design and build an 8 inch SMIF foundry, managed the tool layout for optimum wafer movements, managed the process transfer from technology partner, handled the Quality and Reliability engineering and the FA laboratory. Put together a yield engineering team and set the direction. managed the TCM and TGM efforts, Managed the tool install for phase 1.

As Vice President of Engineering for SUBMICRON TECHNOLOGY PCL. Bangkok Thailand, was responsible for managing and providing the vision and guidance for the following engineering groups; process engineering, yield engineering, product and test engineering, Quality and Reliability engineering, process development and integration engineering.

Previously at INTEL, Inc / Chandler, AZ. Positions included: Manager, Quality and Reliability / Device Engineering Manager / Program Manager. Responsible for managing a group of engineers assigned to develop and execute qualification plans for all new product and process introductions. Yield enhancement and defect density reduction efforts for maximum factory productivity. Analyzed all failed units (from the field, qualification and or reliability monitor) and communicated results back to the factory for root cause analysis. Translated Intel requirements to foundry personnel to transfer Best Known Methods and manufacturing expertise to foundries. Worked with several foundries to develop similar reporting methods as Intel. Supervised SPC implementation and Cpk improvement. Created cost reduction and manufacturing productivity improvement programs. Defined reliability screen requirements for all process changes. Developed and oversaw programs for parametric testing to predict yield and reliability performance.

Previous Experience includes:
GTE, Inc. / Tempe, AZ: Manager Design -Product Engineering, MOTOROLA, Inc. / Mesa AZ: Various positions from design engineer to Yield Enhancement Manager. Start-up team MOS 5, MOS 6, TMOS, dynamic and static RAMs, APRDL. BOWMAR, Inc. / Chandler, / AZ: Manager MOS Circuit Design

EDUCATION
MSEE Degree: Arizona State University / Tempe AZ
BSEE Degree: University of Arizona / Tucson AZ

Additional Training
Workshop for Effective Management; Motorola, Accelerated Life Testing Workshop; Technology Associates, Managerial Accounting; Arizona State University